Eleftheria Litou
Electrical & Computer Engineering student with strong interests in EDA, ASIC, and FPGA design
Final-year Electrical & Computer Engineering student with strong interests in EDA, ASIC, and FPGA design.
Experienced in VLSI design, CAD implementations, TCAD Simulations, and full ASIC flow (frontend and backend),
with hands-on exposure to circuit robustness analysis under radiation-induced effects. Skilled in C/C++, Verilog, and
familiar with digital design flow concepts such as STA, synthesis, CTS, floorplanning, partitioning, placement, and
routing.
Beyond the lab, I have dedicated the last 6 years to the IEEE student community in Volos. Currently serving as the
Head of the IEEE WIE (Women in Engineering) Student Branch of the University of Thessaly in Volos. I previously
spent over four years as the PR Manager for both IEEE and WIE. These roles have shaped my firm belief in gender
equality, peace, and the power of professional friendship as catalysts for innovation.
Additionally, I have contributed as a volunteer to numerous conferences and actively support the academic process
as a volunteer teaching assistant for university courses. When I’m not optimizing circuits or leading team initiatives, I
recharge through dancing, listening to music, reading books or hanging out with friends.
Sessions
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20 May Wed
Presentation of University of Thessaly
Central Library Hall, Aristotle University of Thessaloniki04:00 PM - 06:00 PM
Satellite Event